{
  "url": "https://openlegislation.uk/customs-duties-spain-order-1988/schedule-4",
  "json_url": "https://openlegislation.uk/customs-duties-spain-order-1988/schedule-4.json",
  "legislation": "uksi/1988/1261",
  "legislation_title": "The Customs Duties (Spain) Order 1988",
  "legislation_url": "https://openlegislation.uk/customs-duties-spain-order-1988",
  "path": "schedule/4",
  "kind": "schedule",
  "number": "4",
  "heading": "PARTIAL EXEMPTIONS FROM CUSTOMS DUTIES",
  "text": "Combined nomenclature code\nDescription of Goods\nRates of duty\n(1)\n(2)\n(3)\nas from 10.8.88\nas from 1.1.89\nas from 1.1.90\nas from 1.1.91\nas from 1.1.92\nas from 1.1.93\nas from 1.1.94\nas from 1.1.95\nex 0302.65.10 and ex 0303.75.10\nPiked dogfish (Squalus acanthias), fresh, chilled or frozen, whole, headless or in pieces.\n3.7\n3\n2.2\n0\nex 0306.13.90\nShrimps of the species “Royal Red” (Haliporoides sibogae or Hymenopenaeus sibogae) peeled and deep-frozen, intended for the processing industry for the manufacture of products falling within heading No 1605 (1)\n5.6\n4.5\n3.3\n2.2\n0\nex 0904.20.10\nSweet red or green peppers, in pieces, with a moisture content not exceeding 9.5%\n6.2\n5\n3.7\n2.5\n0\nex 1507.90.10\nPurified soya-bean oil in glass bottles. Each bottle holds 10 litres of purified soya bean oil containing by weight:\na minimum of 8.5% and a maximum of 12% of palmitic acid esters,\na minimum of 2.5% and a maximum of 4.7% of stearic acid esters,\na minimum of 22.4% and a maximum of 29% of oleic acid esters,\na minimum of 46.6% and a maximum of 53.7% of linoleic acid esters,\na minimum of 7.4 % and a maximum of 11% of linolenic acid esters,\nand containing:\nnot more than 5 millimoles of free fatty acid per kilogram of oil,\nphosphalipids corresponding to a nitrogen content not exceeding 0.04 mg per gram of oil.\nThe soya-bean oil covered by this description is destined for the preparation of emulsions for injections (1)\n8 with a maximum duty of 125 ECU per 100 kg\n8 with a maximum duty of 125 ECU per 100 kg\n8 with a maximum duty of 125 ECU per 100 kg\n6.6 with a maximum duty of 104.1 ECU per 100 kg\n5.3 with a maximum duty of 83.2 ECU per 100 kg\n3.9 with a maximum duty of 62.3 ECU per 100 kg\n2.6 with a maximum duty of 41.5 ECU per 100 kg\n1.3 with a maximum duty of 20.6 ECU per 100 kg\nex 1605.20.00\nShrimps and prawns of the species Pandalus borealis boiled in water and shelled, whether or not frozen or dried, intended for the industrial processing of products falling within heading No 1605 (1)\n5.4\n4.2\n3.1\n2.1\n0\nex 1605.30.00\nLobster flesh, cooked, to be used by the processing industry for the manufacture of butters based on lobster, pastes, pâtés, soups or sauces (1) (2)\n3.1\n2.5\n0\nex 2926.90.90\nIsophthalonitrile\n2.2\n0\nex 2933.51.10\nPhenobarbital (INN) and its salts\n2.7\n0\nex 3906.90.00\nPolymerization products of acrylic acid with small quantities of a polyunsaturated monomer, for use as a stabilizer in emulsions or dispersions with a pH of more than 13 (a)\n2.2\n0\nex 8541.40.10 and ex 8542.20.00\nDigital display of a size not exceeding 25×35 mm, consisting of a printed circuit board on which are mounted, under a plastic cover, up to 22 light-emitting diodes manufactured from gallium-based semiconductor compounds. Each display consists of a single character with or without a plus or minus sign and/or one or two dots\n2.6\n0\nex 8542.11.71\nStatic, random-access memory of C-MOS technology (C-MOS S-RAM) with a storage capacity of 2 K×8 bits and with a nominal standby power of 0,005 milliwatts at 25°C in the form of a monolithic integrated circuit, contained in a housing the exterior dimensions of which do not exceed 17×33 mm with not more than 24 connecting pins and bearing:\nan identification marking consisting of or including one of the following combinations of figures and letters\nTC5516APL-2\nTC5517CPL-15\nTC5516AFL-2\nTC5517CPL-20\nTC5516APL\nTC5517CFL-15\nTC65516AFL\nTC5517CFL-20\nTC5517BPL-20\nTC5517BPL-25\nTC5517BFL-20\nTC65517BFL-25\nor\nother identification markings relating to C-MOS S-RAMs complying with the abovementioned description\n2.6\n0\nex 8542.11.71\nNon-volatile memory in the form of a monolithic integrated circuit, consisting of a C-MOS S-RAM, with a capacity of 16 Kbits and internal power supply, contained in a housing the exterior dimensions of which do not exceed 19×36 mm, with not more than 28 connecting pins and bearing:\nan identification marking consisting of or including one of the following combinations of figures and letters:\nDS 1220 Y\nMK 48 Z 02 (B)\nor\nother identification markings relating to non-volatile memories complying with the abovementioned description\n2.6\n0\nex 8542.11.71\nStatic, random-access memory of C-MOS technology (C-MOS S-RAM) with a storage capacity of 2 K×8 bits and with a nominal standby power of 0,005 milliwatts at 25°C in the form of a monolithic integrated circuit, contained in a housing the exterior dimensions of which do not exceed 17×33 mm with not more than 24 connecting pins and bearing:\nan identification marking consisting of or including one of the following combinations of figures and letters:\nTC5516APL-2\nTC5517CPL-15\nTC5516AFL-2\nTC5517CPL-20\nTC5516APL\nTC5517CFL-15\nTC65516AFL\nTC5517CFL-20\nTC5517BPL-20\nTC5517BPL-25\nTC5517BFL-20\nTC65517BFL-25\nor\nother identification markings relating to C-MOS S-RAMs complying with the abovementioned description\n2.6\n0\nex 8542.11.71\nDynamic, random-access read/write memory of N-MOS (including H-MOS) technology, (N-MOS D-RAMs) with a storage capacity of 64 K×4 bits, in the form of a monolithic integrated circuit, contained in a housing the exterior dimensions of which do not exceed 17×34 mm, with not more than 20 connecting pins arranged in two parallel lines (dual-in-line package) and bearing:\nan identification marking consisting of or including one of the following combinations of figures and letters:\nHM 50464\nPD 41464\nMSM 4464\nTMM 41464\nMB 81464\nTMS 4464\nPD 41254\nor\nother identification markings relating to N-MOS D-RAMs complying with the abovementioned description\n3.7\n2.8\n2.1\n0\nex 8542.11.71\nDynamic random-access memories (D-RAMs), of N-MOS (including H-MOS) technology with a storage capacity of 256 K bits and access times not exceeding 150 ns, in the form of a monolithic integrated circuit, contained in a housing the exterior dimensions of a which do not exceed 12×22 mm, with not more than 20 connecting pins with zig-zag in-line package and bearing:\nan identification marking consisting of or including one of the following combinations of figures and letters:\nHM 50256 ZP\nMB 81256 P\nPD 41256 V\nor\nother identification markings relating to components complying with the abovementioned description\n3.7\n2.8\n2.1\n0\nex 8542.11.71\nRead-only memory in C-MOS technology (C-MOS ROM) with a storage capacity of 256 K bits and a standby current of not more than 0,03 mA, in the form of a monolithic integrated circuit contained in a housing the exterior dimensions of which do not exceed 17×50 mm, with not more than 54 connecting pins and bearing:\nan indentification marking consisting of or including one of the following combinations of figures and letters:\nHN 61256\nHN 613256\nMB 83256\nor\nother identification markings relating to C-MOS ROMs complying with the abovementioned description\n2.6\n0\nex 8542.11.71\nRead-only memory of C-MOS technology (C-MOS ROM) with a storage capacity of one megabit in the form of a monolithic integrated circuit contained in a housing the exterior dimensions of which do not exceed 17×39 mm, with not more than 28 connecting pins and bearing:\nan identification marking consisting of or including one of the following combinations of figures and letters:\nHN 62301 P\nMB 83 1000\nMB 831124\nTC 53 1000 P\nor\nother identification markings relating to C-MOS ROMs complying with the abovementioned description\n2.6\n0\nex 8542.11.75\nSingle-chip 8-bit microcomputer of N-MOS (including H-MOS) technology, in the form of a monolithic integrated circuit incorporating 16-bit arithmetic/logic unit (ALU), 4 K bits ROM, 2 K bits RAM, contained in a housing the external dimensions of which do not exceed 42×17 mm with not more than 64 connecting pins and bearing:\nan identification marking consisting of or including the following combination of figures and letters:\nPD 7811 G\nor\nother identification markings relating to microcomputers complying with the abovementioned description\n3.7\n2.8\n2.1\n0\nex 8542.11.75\n8-bit microprocessor of N-MOS (including H-MOS) technology with 16 bit internal architecture, in the form of a monolithic integrated circuit consisting of a central processing unit (CPU), a timing generator, two independent DMA channels, a programmable interrupt controller, three programmable 16 bit timers, programmable memory and peripheral chip select, a programmable wait state generator and a local bus controller, contained in a housing the dimensions of which do not exceed 30×30 mm with not more than 68 connecting pins or contact areas, and bearing:\nan identification marking consisting of or including the following combination of figures:\n80188\nor\nother identification markings relating to microprocessors complying with the abovementioned description\n2.6\n0\nex 8542.11.75\n16-bit microprocessor of N-MOS technology (including H-MOS) in the form of a monolithic integrated circuit, consisting of a central processing unit (CPU), a memory management and protection unit (MMU) and a real address and virtual address operating mode system (OSO), contained in a housing whose exterior dimensions do not exceed 30×30 mm, with not more than 68 connecting pins or contact areas and bearing:\nand identification marking consisting of or including the following combination of figures:\n80286\nor\nother identification markings relating to microprocessors complying with the abovementioned description\n3.7\n2.8\n2.1\n0\nex 8542.11.75\nGraphics co-processor of C-MOS technology comprising an advanced DRAM controller for graphics memory, shift registers and DMA channel, up to 256 simultaneous colours, multi-tasking support, integral sequential DRAM/access DRAMs, contained in a housing the exterior dimensions of which do not exceed 37×37 mm, with not more than 88 connecting pins or contact areas and bearing:\nan identification marking consisting of or including the following combination of figures:\n82786\nor\nother identification markings relating to graphics co-processors complying with the abovementioned description\n2.6\n0\nex 8542.11.91\nSemi-custom logic array (gate array) of C-MOS technology with metal gates, in the form of a monolithic integrated circuit with an operating voltage of 12 volts, with not less than 637 two-input functions, having within the array a digital code produced by an electron beam, contained in a housing whose exterior dimensions do not exceed 29×11 mm, with not more than 22 connecting pins and bearing:\nan identification marking consisting of or including the following combination of figures and letters:\nFB 215\nor\nother identification markings relating to gate arrays complying with the abovementioned description\n2.6\n0\nex 8542.11.91\nGate arrays of C-MOS technology in the form of a monolithic integrated circuit containing not less than 100 K transistors and not more than 500,000 transistors, contained in a housing the exterior dimensions of which do not exceed 50×50 mm, with not more than 299 connecting pins and bearing:\nan identification consisting of or including one of the following combinations of figures and letters:\nLCA 10026\nLCA 10075\nLCA 10038\nLCA 10100\nLCA 10051\nLCA 10129\nor\nother identification markings relating to microprocessors complying with the abovementioned description\n2.6\n0\nex 8542.11.91\nFloppy disc controller of C-MOS technology, in the form of a monolithic integrated circuit contained in a housing the exterior dimensions of which do not exceed 16×62 mm, with not more than 48 connecting pins and bearing:\nan identification marking consisting of or including one of the following combinations of letters and figures:\nFE 2100\nG 70360-33\nL 1 A 0519\nMB 89311\nWD 16 C 92\nWD 37 C 65\nor\nother identification markings relating to adaptor circuits complying with the abovementioned description\n2.6\n0\nex 8542.11.91\nCathode-ray tube controller (CRTC) of N-MOS (including H-MOS) technology in the form of a monolithic integrated circuit contained in a housing the exterior dimensions of which do not exceed 62×25 mm, with not more than 68 connecting pins and bearing:\nan identification marking either consisting of or including one of the following combinations of figures and letters:\nAM 8052\nD 8275 H\nHD 6845\nHD 68 A 45\nP 8275 H\nor\nother identification markings relating to CRTCs complying with the abovementioned description\n2.6\n0\nex 8542.11.91\nProgrammable advanced video display controller (AVDGs) of N-MOS (including H-MOS) technology in the form of a monolithic integrated circuit, contained in a housing whose external dimensions do not exceed 15×55 mm, with not more than 40 connecting pins and bearing:\nan identification marking consisting of or including the following combination of figures and letters:\nSCN 2674\nor\nother identification markings relating to controllers complying with the abovementioned description\n2.6\n0\nex 8542.11.91\nProgrammable communication interface of N-MOS (including H-MOS) technology (N-MOS PCIs), in the form of amonolithic integrated circuit, containedin a housing the exterior dimensions ofwhich do not exceed 17×39 mm, withnot more than 28 connecting pins andbearing:\nan identification marking consistingof or including the following combiation of figures and letters:\n8251 A\nor\nother identification markings relatingto N-MOS PCIs complying with theabovementioned description\n2.6\n0\nex 8542.11.91\nMonolithic integrated circuit with at least 16 analogue switching elements, of C-MOS technology, for controlling low frequency signals in the range of 20 Hz to 20,000 Hz, capable of dealing with signals up to 3 V with a distortion of not more than 0.05% over the whole frequency range at a voltage of 1 V, contained in a housing the exterior dimensions of which do not exceed 16×40 mm, with not more than 42 connecting pins and bearing:\nan identification marking consisting of or including one of the following combinations of figures and letters:\nTC 9164 N\nTC 9177 P\nTC 9184 P\nor\nother identification markings relating to monolithic integrated circuits complying with the abovementioned description\n2.6\n0\nex 8542.11.99\nUniversal synchronous/asynchronous receiver/transmitter (USART) of C-MOS technology, in the form of a monolithic integrated circuit, contained in a housing the exterior dimensions of which do not exceed 17×39 mm, with not more than 32 connecting pins or contact areas and bearing:\nan identification marking consisting of or including the following combination of figures and letters:\nMSM 82 C 51\nor\nother identification markings relating to universal synchronous/asynchronous receiver/transmitters complying with the abovementioned description\n2.6\n0\nex 8542.11.99\nPulse code modulation (PCM) codec of N-MOS (including H-MOS) technology, in the form of a monolithic integrated circuit, consisting of a sample and hold circuit digital-to-analogue converter, comparator, successive approximation register and logic function to interface to a fall duplex PCM link, contained in a housing whose exterior dimensions do not exceed 11×29 mm, with not more than 22 connecting pins and bearing:\nan identification marking consisting of or including the following combination of figures and letters:\n2911 A-1\nor\nother identification markings relating to PCM codecs complying with the abovementioned description\n2.6\n0\nex 8542.11.99\nSubscriber line audio-processing circuit (SLAC) with two digital signal processors, an anlogue-digital converter and a digital-analogue converter, in the form of a monolithic integrated circuit, contained in a housing the exterior dimensions of which do not exceed 17×39 mm, with not more than 28 connecting pins and bearing:\nan identification marking consisting of or including one of the following combinations of figures and letters:\nAM 7901\nAM 7905\nor\nother identification markings relating to SLACs complying with the abovementioned description\n2.6\n0\nex 8542.11.99\nPulse code modulation (PCM) transmit/receive filter of N-MOS (including H-MOS) technology, in the form of a monolithic integrated circuit, consisting of two filters of a PCM line or trunk termination, contained in a housing whose exterior dimensions do not exceed 10×21 mm, with not more than 16 connecting pins and bearing:\nan identification marking consisting of or including the following combination of figures and letters:\nD 2912 A\nor\nother identification markings relating to PCM filters complying with the abovementioned description\n2.6\n0",
  "extent": null,
  "status": null,
  "version": "current",
  "annotations": [],
  "outstanding_effects": [],
  "provenance": {
    "source": "legislation.gov.uk",
    "source_url": "https://www.legislation.gov.uk/uksi/1988/1261/schedule/4",
    "retrieved_at": "2026-10-29T16:03:09.401739+00:00"
  },
  "licence": "Open Government Licence v3.0",
  "licence_url": "https://www.nationalarchives.gov.uk/doc/open-government-licence/version/3/",
  "attribution": "Contains public sector information licensed under the Open Government Licence v3.0. Source: legislation.gov.uk, The National Archives."
}