# Council Regulation (EC) No 428/2009 of 5 May 2009 setting up a Community regime for the control of exports, transfer, brokering and transit of dual-use items (Recast), Division: CATEGORY 4 — COMPUTERS

Extent: E+W+S+N.I.

Note 1: Computers, related equipment and "software" performing telecommunications or "local area network" functions must also be evaluated against the performance characteristics of Category 5, Part 1 (Telecommunications).
Note 2: Control units which directly interconnect the buses or channels of central processing units, ‘main storage’ or disk controllers are not regarded as telecommunications equipment described in Category 5, Part 1 (Telecommunications).
NB: For the control status of "software" specially designed for packet switching, see 5D001.
Technical Note:
For the purposes of Note 2, ‘main storage’ is the primary storage for data or instructions for rapid access by a central processing unit. It consists of the internal storage of a "digital computer" and any hierarchical extension thereto, such as cache storage or non-sequentially accessed extended storage.
TECHNICAL NOTE ON "ADJUSTED PEAK PERFORMANCE" ("APP")
"APP" is an adjusted peak rate at which "digital computers" perform 64-bit or larger floating point additions and multiplications.
"APP" is expressed in Weighted TeraFLOPS (WT), in units of 1012 adjusted floating point operations per second.
Abbreviations used in this Technical Note
nnumber of processors in the "digital computer"
iprocessor number (i,...n)
tiprocessor cycle time (ti = 1/Fi)
Fiprocessor frequency
Ripeak floating point calculating rate
Wiarchitecture adjustment factor
Outline of "APP" calculation method
1. For each processor i, determine the peak number of 64-bit or larger floating point operations, FPOi, performed per cycle for each processor in the "digital computer".
Note:In determining FPO, include only 64-bit or larger floating point additions or multiplications. All floating point operations must be expressed in operations per processor cycle; operations requiring multiple cycles may be expressed in fractional results per cycle. For processors not capable of performing calculations on floating point operands of 64-bit or more, the effective calculating rate R is zero.
2. Calculate the floating point rate R for each processor Ri = FPOi/ti.
3. Calculate "APP" as "APP" = W1 × R1 + W2 × R2 + … + Wn × Rn.
4. For ‘vector processors’, Wi = 0,9. For non-‘vector processors’, Wi = 0,3.
Note 1:For processors that perform compound operations in a cycle, such as addition and multiplication, each operation is counted.
Note 2:For a pipelined processor the effective calculating rate R is the faster of the pipelined rate, once the pipeline is full, or the non-pipelined rate.
Note 3:The calculating rate R of each contributing processor is to be calculated at its maximum value theoretically possible before the "APP" of the combination is derived. Simultaneous operations are assumed to exist when the computer manufacturer claims concurrent, parallel, or simultaneous operation or execution in a manual or brochure for the computer.
Note 4:Do not include processors that are limited to input/output and peripheral functions (e.g., disk drive, communication and video display) when calculating "APP".
Note 5:"APP" values are not to be calculated for processor combinations (inter)connected by "Local Area Networks", Wide Area Networks, I/O shared connections/devices, I/O controllers and any communication interconnection implemented by "software".
Note 6:"APP" values must be calculated for processor combinations containing processors specially designed to enhance performance by aggregation, operating simultaneously and sharing memory.
Technical Notes:
1.Aggregate all processors and accelerators operating simultaneously and located on the same die.
2.Processor combinations share memory when any processor is capable of accessing any memory location in the system through the hardware transmission of cache lines or memory words, without the involvement of any software mechanism, which may be achieved using "electronic assemblies" specified in 4A003.c.
Note 7:A ‘vector processor’ is defined as a processor with built-in instructions that perform multiple calculations on floating-point vectors (one-dimensional arrays of 64-bit or larger numbers) simultaneously, having at least 2 vector functional units and at least 8 vector registers of at least 64 elements each.

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Source: https://www.legislation.gov.uk/eur/2009/428/annex/I/division/6 (the official version)
Page: https://openlegislation.uk/eu-regulation-2009-428/annex-I/division-6
Contains public sector information licensed under the Open Government Licence v3.0. Source: legislation.gov.uk, The National Archives.