{
  "url": "https://openlegislation.uk/export-control-amendment-no-2-regulations-2025/regulation-9",
  "json_url": "https://openlegislation.uk/export-control-amendment-no-2-regulations-2025/regulation-9.json",
  "legislation": "uksi/2025/1197",
  "legislation_title": "The Export Control (Amendment) (No. 2) Regulations 2025",
  "legislation_url": "https://openlegislation.uk/export-control-amendment-no-2-regulations-2025",
  "path": "regulation/9",
  "kind": "regulation",
  "number": "9",
  "heading": "Amendments to Category 3 - Electronics",
  "text": "(1) The section headed Category 3 - Electronics is amended as follows.\n(2) In the section headed 3A Systems, Equipment and Components—\n(a) in Note 1, for “or 3A001.b.12.,” substitute “3A001.b.12. or 3A501.a.15.”;\n(b) after the Technical Note to 3A001.a.2., insert—\n“N.B.:\nFor cryogenic CMOS integrated circuits not specified in 3A001.a.2., see 3A501.a.15.”;\n(c) after the Note to entry 3A001.a.7., for the N.B. substitute—\n“N.B.1.:\nFor integrated circuits having field programmable logic devices that are combined with an analogue-to-digital converter, see 3A001.a.14.\nN.B.2.:\nFor “electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs), see 3A502.i.”;\n(d) after entry 3A001.a.9., insert—\n“N.B.:\nFor integrated circuits, having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more, see 3A501.a.16.”;\n(e) after entry 3A234, insert—\n“\n3A501\nElectronic items, as follows:\na.\nGeneral purpose integrated circuits, as follows:\n15.\nComplementary Metal Oxide Semiconductor (CMOS) integrated circuits, not specified in 3A001.a.2., designed to operate at an ambient temperature equal to or less (better) than 4,5 K (-268,65°C).\nTechnical Note:\nFor the purposes of 3A501.a.15., CMOS integrated circuits are also referred to as cryogenic CMOS or cryoCMOS integrated circuits.\n16.\nIntegrated circuits having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more.\nN.B.:\nFor “digital computers” and “electronic assemblies” containing integrated circuits specified in 3A501.a.16., see 4A507.\nTechnical Notes:\nFor the purposes of 3A501.a.16.:\n1.\n'Total processing performance' ('TPP') is 2 x 'MacTOPS' x 'bit length of the operation', aggregated over all processing units on the integrated circuit.\na.\n'MacTOPS' is the theoretical peak number of tera (1012) operations per second for multiply-accumulate computation, D=AxB+C).\nb.\nThe 2 in the 'TPP' formula is based on the industry convention of counting one multiply-accumulate computation, D=AxB+C, as 2 operations for the purpose of datasheets. Therefore, 2 x MacTOPS may correspond to the reported TOPS or FLOPS on a datasheet.\nc.\n'Bit length of the operation' for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation.\nd.\nAggregate the TPPs for each processing unit on the integrated circuit to arrive at a total. 'TPP' = TPP1 + TPP2 +… + TPPn (where n is the number of processing units on the integrated circuit).\n2.\nThe rate of 'MacTOPS' is to be calculated at its maximum value theoretically possible. The rate of 'MacTOPS' is assumed to be the highest value the manufacturer claims in a manual or brochure for the integrated circuit. For example, the 'TPP' threshold of 6 000 can be met with 750 tera integer operations (or 2 x 375 'MacTOPS') at 8 bits or 300 tera FLOPS (or 2 x 150 'MacTOPS') at 16 bits. If the IC is designed for MAC computation with multiple bit lengths that achieve different 'TPP' values, the highest 'TPP' value should be evaluated against parameters in 3A501.a.16.\n3.\nFor integrated circuits, specified in 3A501.a.16., that provide processing of both sparse and dense matrices, the 'TPP' values are the values for processing of dense matrices (e.g., without sparsity).\nb.\nMicrowave or millimetre wave items as follows:\n13.\nParametric signal amplifiers having all of the following:\na.\nDesigned for operation at an ambient temperature below 1 K (-272,15ºC);\nb.\nDesigned for operation at any frequency from 2 GHz up to and including 15 GHz; and\nc.\nA noise figure less (better) than 0,015 dB at any frequency from 2 GHz up to and including 15 GHz at 1 K (-272,15ºC);\nNote:\nParametric signal amplifiers include Travelling Wave Parametric Amplifiers (TWPAs).\nTechnical Note:\nFor the purposes of 3A501.b.13., parametric signal amplifiers may also be referred to as Quantum-Limited Amplifiers (QLAs).\n3A502\nGeneral purpose “electronic assemblies”, modules and equipment, as follows:\ni.\n“Electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs) and having an ‘aggregate lookup table input count' of greater than or equal to 1 800 000.\nN.B.:\nFor items having FPLDs that are combined with an Analogue-to-Digital Converter (ADC), rated for extended operating temperatures or are radiation hardened, or have cryptographic functionality, see 3A002.h., 4A001.a., and 5A002.a. respectively.\nTechnical Notes:\nFor the purposes of 3A502.i.:\n1.\n'User configurable' means a user can configure or modify the logic cells or interconnects between logic cells within the FPLD logic fabric to prescribe the specific function that the 3A502.i. item performs.\n2.\n'Aggregate lookup table input count' is the sum of the number of independent inputs available to each programmable Lookup Table (LUT), as accumulated across all physical LUTs contained within a FPLD or other programmable item. An example is: a circuit board containing 2 FPGAs, each having 150 000 programmable LUTs with 6 inputs, would have an 'aggregate lookup table input count' of 2 x 150 000 x 6 = 1 800 000.\n3A504\nCryogenic cooling systems and components, as follows:\na.\nSystems rated to provide a cooling power greater than or equal to 600 μW at or below a temperature of 0,1 K (-273,05°C) for a period of greater than 48 hours;\nb.\nTwo-stage pulse tube cryocoolers rated to maintain a temperature below 4 K (-269,15°C) and provide a cooling power greater than or equal to 1,5 W at or below a temperature of 4,2 K (-268,95°C).\n”.\n(3) In the section headed 3B Test, Inspection and Production Equipment—\n(a) after entry 3B001.a., insert—\n“N.B.:\nFor equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), see 3B501.a.4.”;\n(b) after entry 3B001.f.1., insert—\n“N.B.:\nSEE ALSO 3B501.f.”;\n(c) after entry 3B001.g., insert—\n“N.B.:\nSEE ALSO 3B501.l.”;\n(d) after entry 3B002, insert—\n“\n3B501\nEquipment for the manufacturing of semiconductor devices or materials, as follows and specially designed components and accessories therefor:\na.\nEquipment designed for epitaxial growth as follows:\n1.\nNot used;\n2.\nNot used;\n3.\nNot used;\n4.\nEquipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), and having all of the following:\na.\nAt least one preclean chamber designed to provide a surface preparation means to clean the surface of the wafer; and\nb.\nAn epitaxial deposition chamber designed to operate at a temperature below 958 K (685°C);\nNote:\n3B501.a.4. includes Atomic Layer Epitaxy (ALE) equipment.\nb.\nNot used;\nc.\nNot used;\nd.\nNot used;\ne.\nNot used;\nf.\nLithography equipment as follows:\n1.\nAlign and expose step and repeat (direct step on wafer) or step and scan (scanner) lithography equipment for wafer processing, not specified in 3B001.f., using photo-optical or X-ray methods, and having any of the following:\na.\nA light source wavelength shorter than 193 nm; or\nb.\nHaving all of the following:\n1.\nA light source wavelength equal to or longer than 193 nm;\n2.\nCapable of producing a pattern with a 'Minimum Resolvable Feature size' ('MRF') of 45 nm or less; and\n3.\nA maximum 'dedicated chuck overlay' value of less than or equal to 1,5 nm;\nTechnical Notes:\nFor the purposes of 3B501.f.1.b.:\n1.\nThe 'Minimum Resolvable Feature size' ('MRF') is calculated by the following formula:\n' M R F ' = ( a n e x p o s u r e l i g h t s o u r c e w a v e l e n g t h i n n m ) × ( K f a c t o r ) m a x i m u m n u m e r i c a l a p e r t u r e\nwhere the K factor = 0,25\n'MRF' is also known as resolution.\n2.\n'Dedicated chuck overlay' is the alignment accuracy of a new pattern to an existing pattern printed on a wafer by the same lithographic system.\n'Dedicated chuck overlay' is also known as single machine overlay.\nN.B.:\nSEE ALSO 3B001.f.1.\ng.\nNot used;\nh.\nNot used;\ni.\nNot used;\nj.\nNot used;\nk.\nEquipment designed for dry etching having any of the following:\n1.\nEquipment designed or modified for isotropic dry etching, having a largest 'silicon germanium-to-silicon (SiGe:Si) etch selectivity' of greater than or equal to 100:1; or\n2.\nEquipment designed or modified for anisotropic dry etching, having all of the following:\na.\nRadio Frequency (RF) power source(s) with at least one pulsed RF output;\nb.\nOne or more fast gas switching valve(s) with switching time less than 300 ms; and\nc.\nElectrostatic chuck with 20 or more individually controllable variable temperature elements;\nNote 1.:\n3B501.k. includes etching by 'radicals', ions, sequential reactions or non-sequential reactions.\nNote 2.:\n3B501.k. includes etching using RF pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, cyclic injection and purging of gases combined with a plasma, plasma atomic layer etching or plasma quasiatomic layer etching.\nTechnical Notes:\nFor the purposes of 3B501.k.:\n1.\n'Silicon germanium-to-silicon (SiGe:Si) etch selectivity' is measured for a Ge concentration of greater than or equal to 30% (Si0,7 Ge0,3).\n2.\n'Radical' is defined as an atom, molecule or ion that has an unpaired electron in an open electron shell configuration.\nl.\n'Extreme Ultraviolet' ('EUV') masks and 'EUV' reticles, designed for integrated circuits, not specified in 3B001.g., and having a mask “substrate blank” specified in 3B001.j.;\nTechnical Notes:\n1.\nFor the purposes of 3B501.l., masks or reticles with a mounted pellicle are considered masks and reticles.\n2.\nFor the purposes of 3B501.l., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.\nm.\n'Pellicles' specially designed for 'Extreme Ultraviolet' ('EUV') lithography;\nTechnical Notes:\n1.\nFor the purposes of 3B501.m., a 'pellicle' is a membrane integrated with a frame, designed to protect a mask or reticle from particle contamination.\n2.\nFor the purposes of 3B501.m., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.\nn.\nSemiconductor manufacturing deposition equipment as follows:\n1.\nAtomic Layer Deposition (ALD) equipment as follows:\na.\nEquipment designed for the deposition of tungsten to fill an entire interconnect or in a channel less than 40 nm wide;\nb.\nEquipment designed for 'area selective deposition' of a metal or metal nitride sidewall barrier using an organometallic compound precursor;\nTechnical Note:\nFor the purposes of 3B501.n.1.b., 'area selective deposition' refers to the deposition of material on the sidewall but not the bottom of a feature.\nc.\nEquipment designed for the deposition of a 'work function metal' composed of titanium aluminium carbide (TiAlC) and having a work function greater than 4 eV, and having all of the following:\n1.\nMore than one metal source of which one is functioning as an aluminium precursor source; and\n2.\nA precursor vessel designed to operate at a temperature greater than or equal to 303,15 K (30℃);\nTechnical Note:\nFor the purposes of 3B501.n.1.c., 'work function metal' is a material that controls the threshold voltage of a transistor.\n2.\nEquipment designed for cobalt electroplating or cobalt electroless-plating deposition processes;\n3.\nEquipment designed for Chemical Vapour Deposition (CVD) of cobalt fill metal;\n4.\nEquipment designed for 'selective bottom-up' Chemical Vapour Deposition (CVD) of tungsten fill metal;\nTechnical Note:\nFor the purposes of 3B501.n.4., ‘selective bottom-up’ refers to the preferential deposition of material on the bottom relative to the sidewall.\n5.\nEquipment designed for void-free plasma enhanced deposition of a layer with a dielectric constant less than 3,3, in 'gaps' having an 'aspect ratio' equal to or greater than 1:1 and a width less than 25 nm;\nTechnical Notes:\nFor the purposes of 3B501.n.5.:\n1.\nA 'gap' is the space between metal lines.\n2.\nThe 'aspect ratio' (depth : width) is defined as the ratio of the depth to the width of the gap between the metal lines.\n6.\nEquipment designed for the deposition of a ruthenium layer using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);\n7.\nEquipment designed for multistep processing in multiple chambers and maintaining high vacuum or inert environment during transfer between process steps, as follows:\na.\nEquipment designed to fabricate a metal contact by performing all of the following processes:\n1.\nSurface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia, while maintaining the wafer substrate at a temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C);\n2.\nSurface treatment plasma process using oxygen or ozone, while maintaining the wafer substrate at a temperature greater than 313,15 K (40°C) and less than 773,15 K (500°C); and\n3.\nDeposition of a tungsten layer while maintaining the wafer substrate at a temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C);\nb.\nEquipment designed to fabricate a metal contact by performing all of the following processes:\n1.\nSurface treatment plasma process using a remote plasma generator and an ion filter; and\n2.\nDeposition of a cobalt layer selectively onto copper using an organometallic compound precursor;\nc.\nEquipment designed to fabricate a metal contact by performing all of the following processes:\n1.\nDeposition of a titanium nitride or tungsten carbide layer, using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);\n2.\nDeposition of a cobalt layer using a physical sputter deposition technique and having a process pressure greater than 1,33x10 -1 Pa (1 mTorr) and less than 1,33x10 1 Pa (100 mTorr), while maintaining the wafer substrate at temperature less than 773,15 K (500°C); and\n3.\nDeposition of a cobalt layer using an organometallic compound precursor and having a process pressure greater than 1,33x10 2 Pa (1 Torr) and less than 1,33x10 4 Pa (100 Torr), while maintaining the wafer substrate at temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);\nd.\nEquipment designed to fabricate copper interconnects by performing all of the following processes:\n1.\nDeposition of a cobalt or ruthenium layer using an organometallic compound precursor and having a process pressure greater than 1,33x10 2 Pa (1 Torr) and less than 1,33x10 4 Pa (100 Torr), while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C); and\n2.\nDeposition of a copper layer using a physical vapour deposition technique having a process pressure greater than 1,33x10 -1 Pa (1 mTorr) and less than 1,33x10 1 Pa (100 mTorr), while maintaining the wafer substrate at a temperature less than 773,15 K (500°C);\n8.\nEquipment designed to fabricate a metal contact by multistep processing within a single chamber by performing all of the following:\na.\nDeposition of a tungsten layer, using an organometallic compound precursor, while maintaining the wafer substrate temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C); and\nb.\nSurface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia (NH 3).\n3B503\nScanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, having all of the following:\na.\nStage placement accuracy less (better) than 30 nm;\nb.\nStage positioning measurement performed using laser interferometry;\nc.\nPosition calibration within a Field-Of-View (FOV) based on laser interferometer length-scale measurement;\nd.\nCollection and storage of images having more than 2 x 10 8 pixels;\ne.\nFOV overlap of less than 5% in vertical and horizontal directions;\nf.\nStitching overlap of FOV less than 50 nm; and\ng.\nAccelerating voltage more than 21 kV;\nNote 1.:\n3B503 includes SEM equipment designed for chip design recovery.\nNote 2.:\n3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).\n3B504\nCryogenic wafer probing equipment having all of the following:\na.\nDesigned to test devices at temperatures less than or equal to 4,5 K (-268,65°C); and\nb.\nDesigned to accommodate wafer diameters greater than or equal to 100 mm.\n”.\n(4) In the section headed 3C Materials—\n(a) in entry 3C001, for “in PL9013.b. in Schedule 3 to the Export Control Order 2008,” substitute “in 3C507,”;\n(b) in the N.B. to entry 3C005.b., for “‘substrate’” substitute ““substrate””;\n(c) after entry 3C006, insert—\n“\n3C507\nEpitaxial materials consisting of a “substrate” having at least one epitaxially grown layer of any of the following:\na.\nSilicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or\nb.\nGermanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.\n3C508\nFluorides, hydrides, or chlorides of silicon or germanium, containing any of the following:\na.\nSilicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or\nb.\nGermanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.\n3C509\nSilicon, silicon oxides, germanium or germanium oxides, containing any of the following:\na.\nSilicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or\nb.\nGermanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.\nNote:\n3C509 includes “substrates”, lumps, ingots, boules and preforms.\n”.\n(5) In the section headed 3D Software—\n(a) in entry 3D001, after “3A002.h.”, insert “, 3A501.b.13.”;\n(b) in entry 3D002, for “3B001.a. to f., 3B002 or 3A225” substitute “3A225, 3B001.a. to 3B001.f., 3B002, 3B501.a.4., 3B501.f.1., 3B501.k. or 3B501.n.”;\n(c) after entry 3D225, insert—\n“\n3D507\n“Software” designed to extract ‘GDSII’ or equivalent standard layout data and perform layer-to-layer alignment from Scanning Electron Microscope (SEM) images, and generate multi-layer ‘GDSII’ data or the circuit netlist.\nTechnical Note:\nFor the purposes of 3D507, ‘GDSII’ (‘Graphic Design System II’) is a database file format for data exchange of integrated circuit artwork or integrated circuit layout artwork.\n”.\n(6) In the section headed 3E Technology, after entry 3E225, insert—\n“\n3E505\n“ Technology” according to the General Technology Note for the “development”or “production” of integrated circuits or devices, using “Gate-All-Around Field-Effect Transistor” (“GAAFET”) structures.\nNote 1.:\n3E505 includes ‘process recipes’.\nNote 2.:\n3E505 does not control tool qualification or maintenance.\nNote 3.:\n3E505 does not control ‘Process Design Kits’ (‘PDKs’) unless they include libraries implementing functions or technologies for items specified in 3A001 or 3A501.\nTechnical Notes:\n1.\nFor the purposes of 3E505, a ‘process recipe’ is a set of conditions and parameters for a particular process step.\n2.\nFor the purposes 3E505, a ‘Process Design Kit’ (‘PDK’) is a software tool provided by a semiconductor manufacturer to ensure that the required design practices and rules are taken into account in order to successfully produce a specific integrated circuit design in a specific semiconductor process, in accordance with technological and manufacturing constraints (each semiconductor manufacturing process has its particular ‘PDK’).\n”.",
  "extent": null,
  "status": null,
  "version": "current",
  "annotations": [],
  "outstanding_effects": [],
  "provenance": {
    "source": "legislation.gov.uk",
    "source_url": "https://www.legislation.gov.uk/uksi/2025/1197/regulation/9",
    "retrieved_at": "2026-10-28T21:09:38.103283+00:00"
  },
  "licence": "Open Government Licence v3.0",
  "licence_url": "https://www.nationalarchives.gov.uk/doc/open-government-licence/version/3/",
  "attribution": "Contains public sector information licensed under the Open Government Licence v3.0. Source: legislation.gov.uk, The National Archives."
}