Regulation 9 Amendments to Category 3 - Electronics

(1)

The section headed Category 3 - Electronics is amended as follows.

(2)

In the section headed 3A Systems, Equipment and Components—

(a)

in Note 1, for “or 3A001.b.12.,” substitute “3A001.b.12. or 3A501.a.15.”;

(b)

after the Technical Note to 3A001.a.2., insert—

“N.B.:

For cryogenic CMOS integrated circuits not specified in 3A001.a.2., see 3A501.a.15.”;

(c)

after the Note to entry 3A001.a.7., for the N.B. substitute—

“N.B.1.:

For integrated circuits having field programmable logic devices that are combined with an analogue-to-digital converter, see 3A001.a.14.

N.B.2.:

For “electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs), see 3A502.i.”;

(d)

after entry 3A001.a.9., insert—

“N.B.:

For integrated circuits, having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more, see 3A501.a.16.”;

(e)

after entry 3A234, insert—

“

3A501 Electronic items, as follows:
a. General purpose integrated circuits, as follows:
15. Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, not specified in 3A001.a.2., designed to operate at an ambient temperature equal to or less (better) than 4,5 K (-268,65°C).

Technical Note:

For the purposes of 3A501.a.15., CMOS integrated circuits are also referred to as cryogenic CMOS or cryoCMOS integrated circuits.

16. Integrated circuits having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more.

N.B.:

For “digital computers” and “electronic assemblies” containing integrated circuits specified in 3A501.a.16., see 4A507.

Technical Notes:

For the purposes of 3A501.a.16.:

1. 'Total processing performance' ('TPP') is 2 x 'MacTOPS' x 'bit length of the operation', aggregated over all processing units on the integrated circuit.
a. 'MacTOPS' is the theoretical peak number of tera (10¹²) operations per second for multiply-accumulate computation, D=AxB+C).
b. The 2 in the 'TPP' formula is based on the industry convention of counting one multiply-accumulate computation, D=AxB+C, as 2 operations for the purpose of datasheets. Therefore, 2 x MacTOPS may correspond to the reported TOPS or FLOPS on a datasheet.
c. 'Bit length of the operation' for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation.
d. Aggregate the TPPs for each processing unit on the integrated circuit to arrive at a total. 'TPP' = TPP1 + TPP2 +… + TPPn (where n is the number of processing units on the integrated circuit).
2. The rate of 'MacTOPS' is to be calculated at its maximum value theoretically possible. The rate of 'MacTOPS' is assumed to be the highest value the manufacturer claims in a manual or brochure for the integrated circuit. For example, the 'TPP' threshold of 6 000 can be met with 750 tera integer operations (or 2 x 375 'MacTOPS') at 8 bits or 300 tera FLOPS (or 2 x 150 'MacTOPS') at 16 bits. If the IC is designed for MAC computation with multiple bit lengths that achieve different 'TPP' values, the highest 'TPP' value should be evaluated against parameters in 3A501.a.16.
3. For integrated circuits, specified in 3A501.a.16., that provide processing of both sparse and dense matrices, the 'TPP' values are the values for processing of dense matrices (e.g., without sparsity).
b. Microwave or millimetre wave items as follows:
13. Parametric signal amplifiers having all of the following:
a. Designed for operation at an ambient temperature below 1 K (-272,15ºC);
b. Designed for operation at any frequency from 2 GHz up to and including 15 GHz; and
c. A noise figure less (better) than 0,015 dB at any frequency from 2 GHz up to and including 15 GHz at 1 K (-272,15ºC);

Note:

Parametric signal amplifiers include Travelling Wave Parametric Amplifiers (TWPAs).

Technical Note:

For the purposes of 3A501.b.13., parametric signal amplifiers may also be referred to as Quantum-Limited Amplifiers (QLAs).

3A502 General purpose “electronic assemblies”, modules and equipment, as follows:
i. “Electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs) and having an ‘aggregate lookup table input count' of greater than or equal to 1 800 000.

N.B.:

For items having FPLDs that are combined with an Analogue-to-Digital Converter (ADC), rated for extended operating temperatures or are radiation hardened, or have cryptographic functionality, see 3A002.h., 4A001.a., and 5A002.a. respectively.

Technical Notes:

For the purposes of 3A502.i.:

1. 'User configurable' means a user can configure or modify the logic cells or interconnects between logic cells within the FPLD logic fabric to prescribe the specific function that the 3A502.i. item performs.
2. 'Aggregate lookup table input count' is the sum of the number of independent inputs available to each programmable Lookup Table (LUT), as accumulated across all physical LUTs contained within a FPLD or other programmable item. An example is: a circuit board containing 2 FPGAs, each having 150 000 programmable LUTs with 6 inputs, would have an 'aggregate lookup table input count' of 2 x 150 000 x 6 = 1 800 000.
3A504 Cryogenic cooling systems and components, as follows:
a. Systems rated to provide a cooling power greater than or equal to 600 μW at or below a temperature of 0,1 K (-273,05°C) for a period of greater than 48 hours;
b. Two-stage pulse tube cryocoolers rated to maintain a temperature below 4 K (-269,15°C) and provide a cooling power greater than or equal to 1,5 W at or below a temperature of 4,2 K (-268,95°C).

”.

(3)

In the section headed 3B Test, Inspection and Production Equipment—

(a)

after entry 3B001.a., insert—

“N.B.:

For equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), see 3B501.a.4.”;

(b)

after entry 3B001.f.1., insert—

“N.B.:

SEE ALSO 3B501.f.”;

(c)

after entry 3B001.g., insert—

“N.B.:

SEE ALSO 3B501.l.”;

(d)

after entry 3B002, insert—

“

3B501 Equipment for the manufacturing of semiconductor devices or materials, as follows and specially designed components and accessories therefor:
a. Equipment designed for epitaxial growth as follows:
1. Not used;
2. Not used;
3. Not used;
4. Equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), and having all of the following:
a. At least one preclean chamber designed to provide a surface preparation means to clean the surface of the wafer; and
b. An epitaxial deposition chamber designed to operate at a temperature below 958 K (685°C);

Note:

3B501.a.4. includes Atomic Layer Epitaxy (ALE) equipment.

b. Not used;
c. Not used;
d. Not used;
e. Not used;
f. Lithography equipment as follows:
1. Align and expose step and repeat (direct step on wafer) or step and scan (scanner) lithography equipment for wafer processing, not specified in 3B001.f., using photo-optical or X-ray methods, and having any of the following:
a. A light source wavelength shorter than 193 nm; or
b. Having all of the following:
1. A light source wavelength equal to or longer than 193 nm;
2. Capable of producing a pattern with a 'Minimum Resolvable Feature size' ('MRF') of 45 nm or less; and
3. A maximum 'dedicated chuck overlay' value of less than or equal to 1,5 nm;

Technical Notes:

For the purposes of 3B501.f.1.b.:

1.
The 'Minimum Resolvable Feature size' ('MRF') is calculated by the following formula:
$' M R F' = \frac{(a n e x p o s u r e l i g h t s o u r c e w a v e l e n g t h i n n m) \times (K f a c t o r)}{m a x i m u m n u m e r i c a l a p e r t u r e}$

where the K factor = 0,25

'MRF' is also known as resolution.

2.
'Dedicated chuck overlay' is the alignment accuracy of a new pattern to an existing pattern printed on a wafer by the same lithographic system.

'Dedicated chuck overlay' is also known as single machine overlay.

N.B.:

SEE ALSO 3B001.f.1.

g. Not used;
h. Not used;
i. Not used;
j. Not used;
k. Equipment designed for dry etching having any of the following:
1. Equipment designed or modified for isotropic dry etching, having a largest 'silicon germanium-to-silicon (SiGe:Si) etch selectivity' of greater than or equal to 100:1; or
2. Equipment designed or modified for anisotropic dry etching, having all of the following:
a. Radio Frequency (RF) power source(s) with at least one pulsed RF output;
b. One or more fast gas switching valve(s) with switching time less than 300 ms; and
c. Electrostatic chuck with 20 or more individually controllable variable temperature elements;

Note 1.:

3B501.k. includes etching by 'radicals', ions, sequential reactions or non-sequential reactions.

Note 2.:

3B501.k. includes etching using RF pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, cyclic injection and purging of gases combined with a plasma, plasma atomic layer etching or plasma quasiatomic layer etching.

Technical Notes:

For the purposes of 3B501.k.:

1. 'Silicon germanium-to-silicon (SiGe:Si) etch selectivity' is measured for a Ge concentration of greater than or equal to 30% (Si_0,7 Ge_0,3).
2. 'Radical' is defined as an atom, molecule or ion that has an unpaired electron in an open electron shell configuration.
l. 'Extreme Ultraviolet' ('EUV') masks and 'EUV' reticles, designed for integrated circuits, not specified in 3B001.g., and having a mask “substrate blank” specified in 3B001.j.;
Technical Notes:
1. For the purposes of 3B501.l., masks or reticles with a mounted pellicle are considered masks and reticles.
2. For the purposes of 3B501.l., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.
m. 'Pellicles' specially designed for 'Extreme Ultraviolet' ('EUV') lithography;
Technical Notes:
1. For the purposes of 3B501.m., a 'pellicle' is a membrane integrated with a frame, designed to protect a mask or reticle from particle contamination.
2. For the purposes of 3B501.m., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.
n. Semiconductor manufacturing deposition equipment as follows:
1. Atomic Layer Deposition (ALD) equipment as follows:
a. Equipment designed for the deposition of tungsten to fill an entire interconnect or in a channel less than 40 nm wide;
b. Equipment designed for 'area selective deposition' of a metal or metal nitride sidewall barrier using an organometallic compound precursor;

Technical Note:

For the purposes of 3B501.n.1.b., 'area selective deposition' refers to the deposition of material on the sidewall but not the bottom of a feature.

c. Equipment designed for the deposition of a 'work function metal' composed of titanium aluminium carbide (TiAlC) and having a work function greater than 4 eV, and having all of the following:
1. More than one metal source of which one is functioning as an aluminium precursor source; and
2. A precursor vessel designed to operate at a temperature greater than or equal to 303,15 K (30℃);

Technical Note:

For the purposes of 3B501.n.1.c., 'work function metal' is a material that controls the threshold voltage of a transistor.

2. Equipment designed for cobalt electroplating or cobalt electroless-plating deposition processes;
3. Equipment designed for Chemical Vapour Deposition (CVD) of cobalt fill metal;
4. Equipment designed for 'selective bottom-up' Chemical Vapour Deposition (CVD) of tungsten fill metal;

Technical Note:

For the purposes of 3B501.n.4., ‘selective bottom-up’ refers to the preferential deposition of material on the bottom relative to the sidewall.

5. Equipment designed for void-free plasma enhanced deposition of a layer with a dielectric constant less than 3,3, in 'gaps' having an 'aspect ratio' equal to or greater than 1:1 and a width less than 25 nm;

Technical Notes:

For the purposes of 3B501.n.5.:

1. A 'gap' is the space between metal lines.
2. The 'aspect ratio' (depth : width) is defined as the ratio of the depth to the width of the gap between the metal lines.
6. Equipment designed for the deposition of a ruthenium layer using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
7. Equipment designed for multistep processing in multiple chambers and maintaining high vacuum or inert environment during transfer between process steps, as follows:
a. Equipment designed to fabricate a metal contact by performing all of the following processes:
1. Surface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia, while maintaining the wafer substrate at a temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C);
2. Surface treatment plasma process using oxygen or ozone, while maintaining the wafer substrate at a temperature greater than 313,15 K (40°C) and less than 773,15 K (500°C); and
3. Deposition of a tungsten layer while maintaining the wafer substrate at a temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C);
b. Equipment designed to fabricate a metal contact by performing all of the following processes:
1. Surface treatment plasma process using a remote plasma generator and an ion filter; and
2. Deposition of a cobalt layer selectively onto copper using an organometallic compound precursor;
c. Equipment designed to fabricate a metal contact by performing all of the following processes:
1. Deposition of a titanium nitride or tungsten carbide layer, using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
2. Deposition of a cobalt layer using a physical sputter deposition technique and having a process pressure greater than 1,33x10 ^-1 Pa (1 mTorr) and less than 1,33x10 ¹ Pa (100 mTorr), while maintaining the wafer substrate at temperature less than 773,15 K (500°C); and
3. Deposition of a cobalt layer using an organometallic compound precursor and having a process pressure greater than 1,33x10 ² Pa (1 Torr) and less than 1,33x10 ⁴ Pa (100 Torr), while maintaining the wafer substrate at temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
d. Equipment designed to fabricate copper interconnects by performing all of the following processes:
1. Deposition of a cobalt or ruthenium layer using an organometallic compound precursor and having a process pressure greater than 1,33x10 ² Pa (1 Torr) and less than 1,33x10 ⁴ Pa (100 Torr), while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C); and
2. Deposition of a copper layer using a physical vapour deposition technique having a process pressure greater than 1,33x10 ^-1 Pa (1 mTorr) and less than 1,33x10 ¹ Pa (100 mTorr), while maintaining the wafer substrate at a temperature less than 773,15 K (500°C);
8. Equipment designed to fabricate a metal contact by multistep processing within a single chamber by performing all of the following:
a. Deposition of a tungsten layer, using an organometallic compound precursor, while maintaining the wafer substrate temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C); and
b. Surface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia (NH ₃).
3B503 Scanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, having all of the following:
a. Stage placement accuracy less (better) than 30 nm;
b. Stage positioning measurement performed using laser interferometry;
c. Position calibration within a Field-Of-View (FOV) based on laser interferometer length-scale measurement;
d. Collection and storage of images having more than 2 x 10 ⁸ pixels;
e. FOV overlap of less than 5% in vertical and horizontal directions;
f. Stitching overlap of FOV less than 50 nm; and
g. Accelerating voltage more than 21 kV;

Note 1.:

3B503 includes SEM equipment designed for chip design recovery.

Note 2.:

3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).

3B504 Cryogenic wafer probing equipment having all of the following:
a. Designed to test devices at temperatures less than or equal to 4,5 K (-268,65°C); and
b. Designed to accommodate wafer diameters greater than or equal to 100 mm.

”.

(4)

In the section headed 3C Materials—

(a)

in entry 3C001, for “in PL9013.b. in Schedule 3 to the Export Control Order 2008,” substitute “in 3C507,”;

(b)

in the N.B. to entry 3C005.b., for “‘substrate’” substitute ““substrate””;

(c)

after entry 3C006, insert—

“

3C507 Epitaxial materials consisting of a “substrate” having at least one epitaxially grown layer of any of the following:
a. Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
b. Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.
3C508 Fluorides, hydrides, or chlorides of silicon or germanium, containing any of the following:
a. Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
b. Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.
3C509 Silicon, silicon oxides, germanium or germanium oxides, containing any of the following:
a. Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
b. Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.

Note:

3C509 includes “substrates”, lumps, ingots, boules and preforms.

”.

(5)

In the section headed 3D Software—

(a)

in entry 3D001, after “3A002.h.”, insert “, 3A501.b.13.”;

(b)

in entry 3D002, for “3B001.a. to f., 3B002 or 3A225” substitute “3A225, 3B001.a. to 3B001.f., 3B002, 3B501.a.4., 3B501.f.1., 3B501.k. or 3B501.n.”;

(c)

after entry 3D225, insert—

“

3D507 “Software” designed to extract ‘GDSII’ or equivalent standard layout data and perform layer-to-layer alignment from Scanning Electron Microscope (SEM) images, and generate multi-layer ‘GDSII’ data or the circuit netlist.

Technical Note:

For the purposes of 3D507, ‘GDSII’ (‘Graphic Design System II’) is a database file format for data exchange of integrated circuit artwork or integrated circuit layout artwork.

”.

(6)

In the section headed 3E Technology, after entry 3E225, insert—

“

3E505 “ Technology” according to the General Technology Note for the “development”or “production” of integrated circuits or devices, using “Gate-All-Around Field-Effect Transistor” (“GAAFET”) structures.

Note 1.:

3E505 includes ‘process recipes’.

Note 2.:

3E505 does not control tool qualification or maintenance.

Note 3.:

3E505 does not control ‘Process Design Kits’ (‘PDKs’) unless they include libraries implementing functions or technologies for items specified in 3A001 or 3A501.

Technical Notes:
1. For the purposes of 3E505, a ‘process recipe’ is a set of conditions and parameters for a particular process step.
2. For the purposes 3E505, a ‘Process Design Kit’ (‘PDK’) is a software tool provided by a semiconductor manufacturer to ensure that the required design practices and rules are taken into account in order to successfully produce a specific integrated circuit design in a specific semiconductor process, in accordance with technological and manufacturing constraints (each semiconductor manufacturing process has its particular ‘PDK’).

”.

3A501	Electronic items, as follows:
	a.	General purpose integrated circuits, as follows:
		15.	Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, not specified in 3A001.a.2., designed to operate at an ambient temperature equal to or less (better) than 4,5 K (-268,65°C).
			Technical Note: For the purposes of 3A501.a.15., CMOS integrated circuits are also referred to as cryogenic CMOS or cryoCMOS integrated circuits.
		16.	Integrated circuits having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more.
			N.B.: For “digital computers” and “electronic assemblies” containing integrated circuits specified in 3A501.a.16., see 4A507.
			Technical Notes: For the purposes of 3A501.a.16.:
			1.	'Total processing performance' ('TPP') is 2 x 'MacTOPS' x 'bit length of the operation', aggregated over all processing units on the integrated circuit.
				a.	'MacTOPS' is the theoretical peak number of tera (10¹²) operations per second for multiply-accumulate computation, D=AxB+C).
				b.	The 2 in the 'TPP' formula is based on the industry convention of counting one multiply-accumulate computation, D=AxB+C, as 2 operations for the purpose of datasheets. Therefore, 2 x MacTOPS may correspond to the reported TOPS or FLOPS on a datasheet.
				c.	'Bit length of the operation' for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation.
				d.	Aggregate the TPPs for each processing unit on the integrated circuit to arrive at a total. 'TPP' = TPP1 + TPP2 +… + TPPn (where n is the number of processing units on the integrated circuit).
			2.	The rate of 'MacTOPS' is to be calculated at its maximum value theoretically possible. The rate of 'MacTOPS' is assumed to be the highest value the manufacturer claims in a manual or brochure for the integrated circuit. For example, the 'TPP' threshold of 6 000 can be met with 750 tera integer operations (or 2 x 375 'MacTOPS') at 8 bits or 300 tera FLOPS (or 2 x 150 'MacTOPS') at 16 bits. If the IC is designed for MAC computation with multiple bit lengths that achieve different 'TPP' values, the highest 'TPP' value should be evaluated against parameters in 3A501.a.16.
			3.	For integrated circuits, specified in 3A501.a.16., that provide processing of both sparse and dense matrices, the 'TPP' values are the values for processing of dense matrices (e.g., without sparsity).
	b.	Microwave or millimetre wave items as follows:
		13.	Parametric signal amplifiers having all of the following:
			a.	Designed for operation at an ambient temperature below 1 K (-272,15ºC);
			b.	Designed for operation at any frequency from 2 GHz up to and including 15 GHz; and
			c.	A noise figure less (better) than 0,015 dB at any frequency from 2 GHz up to and including 15 GHz at 1 K (-272,15ºC);
			Note: Parametric signal amplifiers include Travelling Wave Parametric Amplifiers (TWPAs).
			Technical Note: For the purposes of 3A501.b.13., parametric signal amplifiers may also be referred to as Quantum-Limited Amplifiers (QLAs).
3A502	General purpose “electronic assemblies”, modules and equipment, as follows:
	i.	“Electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs) and having an ‘aggregate lookup table input count' of greater than or equal to 1 800 000.
		N.B.: For items having FPLDs that are combined with an Analogue-to-Digital Converter (ADC), rated for extended operating temperatures or are radiation hardened, or have cryptographic functionality, see 3A002.h., 4A001.a., and 5A002.a. respectively.
		Technical Notes: For the purposes of 3A502.i.:
		1.	'User configurable' means a user can configure or modify the logic cells or interconnects between logic cells within the FPLD logic fabric to prescribe the specific function that the 3A502.i. item performs.
		2.	'Aggregate lookup table input count' is the sum of the number of independent inputs available to each programmable Lookup Table (LUT), as accumulated across all physical LUTs contained within a FPLD or other programmable item. An example is: a circuit board containing 2 FPGAs, each having 150 000 programmable LUTs with 6 inputs, would have an 'aggregate lookup table input count' of 2 x 150 000 x 6 = 1 800 000.
3A504	Cryogenic cooling systems and components, as follows:
	a.	Systems rated to provide a cooling power greater than or equal to 600 μW at or below a temperature of 0,1 K (-273,05°C) for a period of greater than 48 hours;
	b.	Two-stage pulse tube cryocoolers rated to maintain a temperature below 4 K (-269,15°C) and provide a cooling power greater than or equal to 1,5 W at or below a temperature of 4,2 K (-268,95°C).

3B501	Equipment for the manufacturing of semiconductor devices or materials, as follows and specially designed components and accessories therefor:
	a.	Equipment designed for epitaxial growth as follows:
		1.	Not used;
		2.	Not used;
		3.	Not used;
		4.	Equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), and having all of the following:
			a.	At least one preclean chamber designed to provide a surface preparation means to clean the surface of the wafer; and
			b.	An epitaxial deposition chamber designed to operate at a temperature below 958 K (685°C);
		Note: 3B501.a.4. includes Atomic Layer Epitaxy (ALE) equipment.
	b.	Not used;
	c.	Not used;
	d.	Not used;
	e.	Not used;
	f.	Lithography equipment as follows:
		1.	Align and expose step and repeat (direct step on wafer) or step and scan (scanner) lithography equipment for wafer processing, not specified in 3B001.f., using photo-optical or X-ray methods, and having any of the following:
			a.	A light source wavelength shorter than 193 nm; or
			b.	Having all of the following:
				1.	A light source wavelength equal to or longer than 193 nm;
				2.	Capable of producing a pattern with a 'Minimum Resolvable Feature size' ('MRF') of 45 nm or less; and
				3.	A maximum 'dedicated chuck overlay' value of less than or equal to 1,5 nm;
		Technical Notes: For the purposes of 3B501.f.1.b.:
		1.	The 'Minimum Resolvable Feature size' ('MRF') is calculated by the following formula: $' M R F' = \frac{(a n e x p o s u r e l i g h t s o u r c e w a v e l e n g t h i n n m) \times (K f a c t o r)}{m a x i m u m n u m e r i c a l a p e r t u r e}$
			where the K factor = 0,25 'MRF' is also known as resolution.
		2.	'Dedicated chuck overlay' is the alignment accuracy of a new pattern to an existing pattern printed on a wafer by the same lithographic system. 'Dedicated chuck overlay' is also known as single machine overlay.
		N.B.: SEE ALSO 3B001.f.1.
	g.	Not used;
	h.	Not used;
	i.	Not used;
	j.	Not used;
	k.	Equipment designed for dry etching having any of the following:
		1.	Equipment designed or modified for isotropic dry etching, having a largest 'silicon germanium-to-silicon (SiGe:Si) etch selectivity' of greater than or equal to 100:1; or
		2.	Equipment designed or modified for anisotropic dry etching, having all of the following:
			a.	Radio Frequency (RF) power source(s) with at least one pulsed RF output;
			b.	One or more fast gas switching valve(s) with switching time less than 300 ms; and
			c.	Electrostatic chuck with 20 or more individually controllable variable temperature elements;
		Note 1.: 3B501.k. includes etching by 'radicals', ions, sequential reactions or non-sequential reactions.
		Note 2.: 3B501.k. includes etching using RF pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, cyclic injection and purging of gases combined with a plasma, plasma atomic layer etching or plasma quasiatomic layer etching.
		Technical Notes: For the purposes of 3B501.k.:
		1.	'Silicon germanium-to-silicon (SiGe:Si) etch selectivity' is measured for a Ge concentration of greater than or equal to 30% (Si_0,7 Ge_0,3).
		2.	'Radical' is defined as an atom, molecule or ion that has an unpaired electron in an open electron shell configuration.
	l.	'Extreme Ultraviolet' ('EUV') masks and 'EUV' reticles, designed for integrated circuits, not specified in 3B001.g., and having a mask “substrate blank” specified in 3B001.j.;
		Technical Notes:
		1.	For the purposes of 3B501.l., masks or reticles with a mounted pellicle are considered masks and reticles.
		2.	For the purposes of 3B501.l., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.
	m.	'Pellicles' specially designed for 'Extreme Ultraviolet' ('EUV') lithography;
		Technical Notes:
		1.	For the purposes of 3B501.m., a 'pellicle' is a membrane integrated with a frame, designed to protect a mask or reticle from particle contamination.
		2.	For the purposes of 3B501.m., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.
	n.	Semiconductor manufacturing deposition equipment as follows:
		1.	Atomic Layer Deposition (ALD) equipment as follows:
			a.	Equipment designed for the deposition of tungsten to fill an entire interconnect or in a channel less than 40 nm wide;
			b.	Equipment designed for 'area selective deposition' of a metal or metal nitride sidewall barrier using an organometallic compound precursor;
				Technical Note: For the purposes of 3B501.n.1.b., 'area selective deposition' refers to the deposition of material on the sidewall but not the bottom of a feature.
			c.	Equipment designed for the deposition of a 'work function metal' composed of titanium aluminium carbide (TiAlC) and having a work function greater than 4 eV, and having all of the following:
				1.	More than one metal source of which one is functioning as an aluminium precursor source; and
				2.	A precursor vessel designed to operate at a temperature greater than or equal to 303,15 K (30℃);
				Technical Note: For the purposes of 3B501.n.1.c., 'work function metal' is a material that controls the threshold voltage of a transistor.
		2.	Equipment designed for cobalt electroplating or cobalt electroless-plating deposition processes;
		3.	Equipment designed for Chemical Vapour Deposition (CVD) of cobalt fill metal;
		4.	Equipment designed for 'selective bottom-up' Chemical Vapour Deposition (CVD) of tungsten fill metal;
			Technical Note: For the purposes of 3B501.n.4., ‘selective bottom-up’ refers to the preferential deposition of material on the bottom relative to the sidewall.
		5.	Equipment designed for void-free plasma enhanced deposition of a layer with a dielectric constant less than 3,3, in 'gaps' having an 'aspect ratio' equal to or greater than 1:1 and a width less than 25 nm;
			Technical Notes: For the purposes of 3B501.n.5.:
			1.	A 'gap' is the space between metal lines.
			2.	The 'aspect ratio' (depth : width) is defined as the ratio of the depth to the width of the gap between the metal lines.
		6.	Equipment designed for the deposition of a ruthenium layer using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
		7.	Equipment designed for multistep processing in multiple chambers and maintaining high vacuum or inert environment during transfer between process steps, as follows:
			a.	Equipment designed to fabricate a metal contact by performing all of the following processes:
				1.	Surface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia, while maintaining the wafer substrate at a temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C);
				2.	Surface treatment plasma process using oxygen or ozone, while maintaining the wafer substrate at a temperature greater than 313,15 K (40°C) and less than 773,15 K (500°C); and
				3.	Deposition of a tungsten layer while maintaining the wafer substrate at a temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C);
			b.	Equipment designed to fabricate a metal contact by performing all of the following processes:
				1.	Surface treatment plasma process using a remote plasma generator and an ion filter; and
				2.	Deposition of a cobalt layer selectively onto copper using an organometallic compound precursor;
			c.	Equipment designed to fabricate a metal contact by performing all of the following processes:
				1.	Deposition of a titanium nitride or tungsten carbide layer, using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
				2.	Deposition of a cobalt layer using a physical sputter deposition technique and having a process pressure greater than 1,33x10 ^-1 Pa (1 mTorr) and less than 1,33x10 ¹ Pa (100 mTorr), while maintaining the wafer substrate at temperature less than 773,15 K (500°C); and
				3.	Deposition of a cobalt layer using an organometallic compound precursor and having a process pressure greater than 1,33x10 ² Pa (1 Torr) and less than 1,33x10 ⁴ Pa (100 Torr), while maintaining the wafer substrate at temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
			d.	Equipment designed to fabricate copper interconnects by performing all of the following processes:
				1.	Deposition of a cobalt or ruthenium layer using an organometallic compound precursor and having a process pressure greater than 1,33x10 ² Pa (1 Torr) and less than 1,33x10 ⁴ Pa (100 Torr), while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C); and
				2.	Deposition of a copper layer using a physical vapour deposition technique having a process pressure greater than 1,33x10 ^-1 Pa (1 mTorr) and less than 1,33x10 ¹ Pa (100 mTorr), while maintaining the wafer substrate at a temperature less than 773,15 K (500°C);
		8.	Equipment designed to fabricate a metal contact by multistep processing within a single chamber by performing all of the following:
			a.	Deposition of a tungsten layer, using an organometallic compound precursor, while maintaining the wafer substrate temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C); and
			b.	Surface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia (NH ₃).
3B503	Scanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, having all of the following:
	a.	Stage placement accuracy less (better) than 30 nm;
	b.	Stage positioning measurement performed using laser interferometry;
	c.	Position calibration within a Field-Of-View (FOV) based on laser interferometer length-scale measurement;
	d.	Collection and storage of images having more than 2 x 10 ⁸ pixels;
	e.	FOV overlap of less than 5% in vertical and horizontal directions;
	f.	Stitching overlap of FOV less than 50 nm; and
	g.	Accelerating voltage more than 21 kV;
Note 1.: 3B503 includes SEM equipment designed for chip design recovery.
Note 2.: 3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).
3B504	Cryogenic wafer probing equipment having all of the following:
	a.	Designed to test devices at temperatures less than or equal to 4,5 K (-268,65°C); and
	b.	Designed to accommodate wafer diameters greater than or equal to 100 mm.

3C507	Epitaxial materials consisting of a “substrate” having at least one epitaxially grown layer of any of the following:
	a.	Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
	b.	Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.
3C508	Fluorides, hydrides, or chlorides of silicon or germanium, containing any of the following:
	a.	Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
	b.	Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.
3C509	Silicon, silicon oxides, germanium or germanium oxides, containing any of the following:
	a.	Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
	b.	Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.
Note: 3C509 includes “substrates”, lumps, ingots, boules and preforms.

3E505	“ Technology” according to the General Technology Note for the “development”or “production” of integrated circuits or devices, using “Gate-All-Around Field-Effect Transistor” (“GAAFET”) structures.
Note 1.: 3E505 includes ‘process recipes’.
Note 2.: 3E505 does not control tool qualification or maintenance.
Note 3.: 3E505 does not control ‘Process Design Kits’ (‘PDKs’) unless they include libraries implementing functions or technologies for items specified in 3A001 or 3A501.
Technical Notes:
1.	For the purposes of 3E505, a ‘process recipe’ is a set of conditions and parameters for a particular process step.
2.	For the purposes 3E505, a ‘Process Design Kit’ (‘PDK’) is a software tool provided by a semiconductor manufacturer to ensure that the required design practices and rules are taken into account in order to successfully produce a specific integrated circuit design in a specific semiconductor process, in accordance with technological and manufacturing constraints (each semiconductor manufacturing process has its particular ‘PDK’).